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ISL6260 DATASHEET PDF

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For information regarding Intersil Corporation and its products, see www. This can be accomplished by allowing the system to achieve thermal equilibrium at full load, and then adjusting Rdrp2 to obtain the appropriate load line slope. The required resistance can be calculated by: As load is further reduced, channel switching frequency will drop, providing optimized efficiency at light loading.

Assuming we desire an overcurrent trip level, Ioc, of 55A, and knowing from the Intel Specification that daatasheet load line slope, Rdroop is 0.

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In order to use such capacitors, the resistors and thermistors surrounding the droop voltage sensing and droop amplifier has to be resized up to 10x to reduce the capacitance by 10x.

This is presented in Figure These are labeled RS and RO. Do not operate at or near the maximum ratings listed for extended is,6260 of time.

VO An input to the IC that reports the local output osl6260. For optimum load line regulation performance, the traces connecting these two pins to the Kelvin sense leads of the processor must be laid out in parallel and away from rapidly rising voltage nodes switching nodes and other noisy traces.

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VSS Signal ground; Connect to local controller ground.

As a rule of thumb we start with the voltage drop across the Rn network, VN, to be 0. These traces should be laid out as noise sensitive traces. Each inductor will have a certain level of DC current flowing through it, this current when multiplied by the DCR of the inductor creates a small DC level of voltage. A low level logic signal on this pin indicates that the micro-processor is in Deeper Sleep Mode.

Table 2 shows the operation modes eatasheet ISLC with combinations of control logic. Dynamic Mode of Operation – Compensation Parameters Considering the voltage regulator as a black box with a voltage source controlled by VID and a series impedance, in order to achieve the 2. Figure 45 shows the thermal throttling feature with hysteresis. When asserted low, indicates a reduced load-current condition.

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Once the board has been laid out, some adjustments may be required to adjust the full load droop voltage. In the example above, the resistance on the DFB pin is Rdrp1 in parallel with Rdrop2, that is, 1k in parallel with 8.

The output voltage could also take a long period of time to settle to its final value. No license is granted by implication or otherwise under any dagasheet or patent rights of Intersil or its subsidiaries. As all the phases shares the same hysteretic window voltage, it also ensures excellent dynamic current balance between phases.

Multiphase Core Regulator For IMVP-6 Mobile CPUs

Intel Mobile Voltage Positioning is a smart voltage regulation. An estimate of the value of the resistor is as shown in Equation A capacitor is added in parallel with RL in order to improve the stability margin of the channel current balance loop. If the output voltage is less than the VID set value by mV or more, a fault will latch after 1ms in that condition.

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Dimensions in for Reference Only. Connect to ground at microprocessor die.

ISL6260 Datasheet PDF

VDD 5V bias power. Precision Multiphase Core Voltage Regulation – 0. Dimensions are in millimeters.

With the same modulator, the switching frequency is reduced at light load conditions resulting higher operation efficiency. It should be noted that the switching frequency in the Electrical Specification Table is tested with isl62260 error amplifier output or Comp datasheey voltage at 2V. A current reduction on NTC pin and 40mV voltage increase on threshold voltage of the comparator in this state.

The first is a slow slew rate, used to reduce inrush current on start-up. Intel Datashdet Voltage Positioning is a smart voltage regulation technology, which effectively reduces power dissipation in Intel Pentium processors. The total current going from NTC pin is 60? We use Equation This is shown in Figure ISLC datasheeg RC filter to sense the average voltage on phase node and forces the average voltage on the phase node to be equal for current balance.

The 3V3 pin allows for a system 3. Once we know the attenuation of the RS and RN network, we can then determine the Droop amplifier Gain required to achieve the load line.